The present invention relates to a ferroelectric memory device; and, more particularly, to a ferroelectric memory device including a ferroelectric layer covering all cell region and a method for manufacturing the same.
Several studies on utility of a ferroelectric material as a capacitor dielectric, have been developed to overcome a limit of refresh in a conventional dynamic random access memory(DRAM) and to achieve a large capacitance. A ferroelectric random access memory (FORAM) is one of e nonvolatile memory devices that can store information at turn-off state and has a rapid operating speed comparable to that of the DRAM.SrBi2Ta2O9 (SBT), Pb (Zrx, Ti1xe2x88x92x)O3 (PZT) or (Bi,La)4Ti3O12 (BLT)is mainly used as a storage material of FeRAM. The ferroelectric material has a dielectric constant being in the order of 102-103 at room temperature and has two stabilized remnant polarization states. Therefore, the ferroelectric material is suitable for applying to a nonvolatile memory device.
A signal is inputted to the nonvolatile memory device adopting ferroelectric material by the change of polarization orientation according to an electric field applied thereto, and a digital signal xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is stored therein by an orientation of remnant polarization when an electric field is removed.
In a FeRAM device adopting SrxBiy(TaiNbj)2O9 (hereinafter, referred to as a SBTN), etc, which have perovskite structure, as a ferroelectric layer in a ferroelectric capacitor besides the above-mentioned PZT and SBT, a top/bottom electrode is formed of any one selected from the group consisting of Pt, Ir, Ru, IrO, RuO and Pt-alloy.
FIG. 1 is a conventional equivalent circuit illustrating a FeRAM having one transistor and one capacitor(1T-1C) structure. In FIG. 1, xe2x80x98Cxe2x80x99 denotes a ferroelectric capacitors, xe2x80x98Qxe2x80x99 denotes a MOS transistor, xe2x80x98WL1 and WL2xe2x80x99 denote word lines connected to a gate of the MOS transistor Q, xe2x80x98BLxe2x80x99 denotes a bit line connected to a source/drain region of the MOS transistor, and xe2x80x98PLxe2x80x99 denotes a plate line connected to a top electrode of the terroelectric capacitor C.
FIG. 2 is a cross-sectional view of the FeRAM shown in FIG. 1.
Referring to FIG. 2, adjacent two transistors are formed on a semiconductor substrate 11. A field oxide layer 12 is formed in a predetermined portion of the semiconductor substrate 11 in order to separate two transistors from another two transistors(not shown).
The transistor is formed according to a usual complementary metal oxide semiconductor (CMOS) process. A gate electrode 13 is formed on the semiconductor substrate 11, and a common connection drain of adjacent two transistors (hereinafter, referred to as a xe2x80x98common drainxe2x80x99) 14A and source 14B of each transistor are formed in the semiconductor substrate at each side of the gate electrode 13.
A first interlayer insulating layer 15 is formed and flattened on the semiconductor substrate 11. The first interlayer insulating layer 15 is formed of a first and a second insulating layer 15A and 15B successively deposited. A bit line 17 is connected to the common drain 14A through a fist contact plug 16 penetrating the first insulating layer 15A, and the bit line 17 is insulated by the second insulating layer 15B.
A second contact plug 18 penetrates the first interlayer insulating layer 15 and is connected the source 143 of each transistor and a bottom electrode 19 of a ferroelectric capacitor.
A bottom electrode 19 and a ferroelectric layer 20 are formed on the first interlayer insulating layer 15 to the same size, and a top electric 21 having smaller size than that of the bottom electrode 19 is formed on the ferroelectric layer 20.
A second interlayer insulating layer 22 covers the ferroelectric capacitor and has opening which exposes the top electrode 21. A plate line 23 is formed to couple to the top electrode through the opening in the second interlayer insulating layer 22.
The conventional ferroelectric capacitor of FeRAM cell shown in FIG. 2 is formed by stacking layers for the bottom electrode 19, the ferroelectric layer 20 and the top electrode 21, successively. Thereafter, the top electrode 21 is etched, and the ferroelectric layer 20 and the bottom electrode 19 are etched using other mask different from a mask for forming the top electrode 21.
In the conventional method, it is difficult to form the top electrode and the bottom electrode to the same size, if the size of a bottom and top electrode is same, a bottom and top electrode can be shorten, so it is hard to obtain safety in a process. Also, it is difficult to form the ferroelectric capacitor with one step etch process because the layers of the ferroelectric capacitor is thick. Furthermore, the etch profile of the ferroelectric capacitor is not vertical but is slant, so there is some limit to reduce the size of the ferroelectric capacitor.
Due to the above-mentioned reason, the size of a top electrode, which determines an electric charge storage capacity of a capacitor, is restricted to be smaller than that of a bottom electrode so that is difficult to obtain enough amount of an electric charge.
In the conventional method, the ferroelectric layer is formed to cover the bottom electrode layer just after forming the bottom electrode layer, so the ferroelectric layer should be etched in an etch process for forming the bottom electrode pattern. In the etch process, the ferroelectric layer is exposed to plasma, and thereby the characteristics of the ferroelectric layer is deteriorated. Therefore, a thermal treatment to recover characteristic of the ferroelectric layer should be performed.
That is, when an etch process for forming the bottom electrode is performed, the portion of ferroelectric layer not covered with the top electrode is inevitably exposed to plasma. At this circumstance of the ferroelectric layer being exposed to plasma, polarization has not have a value of (+) and (xe2x88x92), and according to a condition of the ferroelectric layer being exposed to plasma, a value is fixed into (+) or (xe2x88x92), namely pinning phenomenon is generated. Accordingly, a capacity of the ferroelectric capacitor is reduced extremely.
To solve the above-mentioned problem of the ferroelectric layer being exposed to plasma, the ferroelectric layer is formed on the bottom electrode by a spin coating or liquid source misted chemical deposition (LSMCD) after patterning the bottom electrode.
However, it is difficult to form the ferroelectric layer to a uniform thickness because of a bottom electrode and a topology of sub-layers, which are formed before the bottom electrode. Furthermore, cracks can be generated in a portion of the ferroelectric layer where the bottom electrode is not exist, so it is hard to adopt the spin coating and LSMCD to formed the ferroelectric layer.
In addition, the height of the ferroelectric capacitor formed of the bottom electrode, the ferroelectric layer and the top electrode is over 5500 xc3x85. Therefore, burden of etching is increased, and it becomes more difficult to fill an insulating layer between capacitors and to flat the insulating layers as the cell area is decreased.
With decreasing a cell area, it is hard to form a contact hole between the plate line and the capacitor. There, there is proposed a method of connecting the top electrode directly to the plate line by removing an interlayer insulating layer, which covers the top electrode, with a blanket etching or a chemical mechanical polishing (CMP). However from the above-mentioned method, there may be brought out a problem that a plate line and a bottom electrode are being shorten when the interlayer insulating layer is very thin.
It is, therefore, an object of the present invention to provide a ferroelectric memory device and manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma.
It is, therefore, another object of the present invention to provide a ferroelectric memory device and manufacturing method forming the same capable of preventing decreasing of an electric charge storage capacity according to a limit of an electrode size.
It is, therefore, further another object of the present invention to provide a manufacturing method of a ferroelectric memory device capable of preventing burden of a etching process cause by the height of a capacitor, difficulty in planarization and a shorten between top and bottom electrodes.
In accordance with one aspect of the present invention, there is provided a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, including: a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.
In accordance with another aspect of the present invention, there is provided a method of forming a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, comprising steps of: forming a bottom electrode of the ferroelectric capacitor on a substrate; forming a first insulating layer on the bottom electrode and the substrate; removing the first insulating layer until a top surface of the bottom electrode is exposed, wherein the bottom electrode disposed in the first insulating layer and the top surface of the bottom electrode is planarized with the first insulating layer; forming a ferroelectric layer covering not only the bottom electrode but also all the first area; and forming a top electrode of the ferroelectric capacitor on the terroelectric layer overlapped with the bottom electrode.
In accordance with further another aspect of the present invention, there is provided a method of forming a ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, comprising steps of: forming a first insulating layer on a substrate; a forming an opening in the first insulating layer by selectively etching the first insulating layer; forming a bottom electrode of the ferroelectric capacitor in the opening, wherein a top surface of the bottom electrode is planarized with the first insulating layer; forming a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and forming a top electrode of the ferroelectric capacitor on the ferroelectric layer.